1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to structures of field effect transistors having a short channel length and a manufacturing method thereof.
2. Description of the Background Art
In recent years, there has been rapid progress in microminiaturization of elements, which form large scale integrated circuits (LSI's), with the development of integration of semiconductor devices. As one type of element forming the semiconductor devices, there is a field effect transistor. MOS transistors having particularly short channel lengths, which are formed by microminiaturization of these field effect transistors, have such characteristics that an electric field in a channel direction remarkably increases in the proximity of the drain if the drain voltage is increased. Even if the drain voltage is constant, when the difference in the impurity concentrations between the drain region and the substrate region is large, the area of a depletion layer formed in a region therebetween becomes narrower, so that the field strength in a channel direction in the depletion layer becomes large. As a result, electrons in a channel region is accelerated by this strong field and is easily brought to a highly energized state. These highly energized electrons will collide with a grid of silicon at the proximity of the drain region to generate a large amount of electron-hole pairs in an avalanche. Among the electrons and the holes generated by this impact ionization, the electrons are attracted by a high drain field and flow into the drain region to form a part of a drain current. The holes are pushed back by the drain field and thus flow into a depletion layer below the channel region to form a part of a substrate current. In this case, the highly energized electrons generated due to the increase in field strength at the proximity of the drain have been called as hot carriers. The generation of the hot carriers adversely affect reliability of the field effect transistor.
In order to reduce the field strength at the proximity of the drain which may cause generation of the hot carriers, conventionally, field effect transistors having LDD (Lightly Diffused Drain) structures have been proposed and practically utilized. FIG. 16 is a sectional view of an n-channel MOS transistor having the LDD structure. Referring to FIG. 16, a p-type silicon substrate 31 has a gate electrode 33 formed thereon with a gate oxide film 32 therebetween. A sidewall oxide film 34 is formed on the side walls of the gate electrode 33. On opposite sides of the gate electrode 33 are formed n-type impurity regions as source region/drain region. These n-type impurity regions include n.sup.- impurity regions 35a and 35b in a low concentration and n.sup.+ impurity regions 36a and 36b in a high concentration. The n.sup.- impurity regions 35a and 35b in a low concentration are formed on the silicon substrate 31 just below the sidewall oxide film 34. The n.sup.+ impurity regions 36a and 36b are formed in a region away from the gate electrode 33, extending to be connected to the n.sup.- impurity regions 35a and 35b, respectively. In this manner, there are formed source/drain regions including the n.sup.- impurity regions 35a and 35b in a low concentration at the proximity of the channel region. When either of the n.sup.- impurity regions 35a and 35b having the low concentration is used as the drain, the field strength at the proximity of the drain is reduced. That is, as the difference in the impurity concentrations between the n.sup.- impurity region 35a and the region of the p-type silicon substrate 31 is small, an area of a depletion layer formed in a region therebetween becomes wide when the n.sup.- impurity region 35a having a low concentration is used as a drain. Therefore, the field strength in a channel direction, i.e., the field strength in the proximity of the drain is reduced.
In the n-channel MOS transistor having the LDD structure shown in FIG. 16, it is assumed that the drain region is formed of the n.sup.- impurity region 35a and n.sup.+ impurity region 36a. It is further assumed that the source region is formed of the n.sup.- impurity region 35b and n.sup.+ impurity region 36b. Suppose that application of a predetermined voltage to the gate electrode 33 causes the electrons as the carriers to move in a direction indicated by an arrow of a solid line in the channel region. In this case, even if the drain region near the channel is formed by the n.sup.- impurity region 35a having a low concentration, the impact ionization causes the electron-hole pairs. Among them, the electrons indicated with circled "-" in the figure are trapped by the sum of the drain field and the field caused by the gate electrode at the lower part of the sidewall oxide film 34. The trapping of the electrons in the sidewall oxide film 34 causes depletion of the carrier on the substrate surface in the n.sup.- impurity region 35a. This increases the resistance of the n.sup.- impurity region 35a with the passage of time. It can be thereby presumed that the carriers moving in the direction indicated by the arrow of a solid line in the channel region do not flow into the n.sup.- impurity region 35a but flow under the n.sup.- impurity region 35a as indicated by an arrow of a dashed line and then into the n.sup.+ impurity region 36a. As a result, a threshold value Vth of the gate voltage is caused to increase and there is caused decrease in a current drive capacity, i.e., deterioration of a current gain .beta..
Various improved LDD structures have been proposed so as to prevent a device deterioration phenomena peculiar to conventional field effect transistors having the LDD structures and thus to improve the resistance to the hot carrier. A field effect transistor having a GOLD (Gate-Overlapped-LDD) structure as one of such improved LDD structures has been proposed in "THE IMPACT OF GATE-DRAIN OVERLAPPED LDD (GOLD) FOR DEEP SUBMICRON VLSI'S" IEDM Tech. Dig. 1987, pp. 38-41. FIG. 17 is a sectional view of an n-channel MOS transistor having the GOLD structure. Referring to FIG. 17, a gate electrode 37 is formed of polysilicon over the p-type silicon substrate 31 with the gate oxide film 32 therebetween. An oxide film 39 is formed on the gate electrode 37 by a CVD method. A sidewall oxide film 40 is formed on the sidewalls of the gate electrode 37. Source and drain regions formed on opposite sides of the electrode 37 include n.sup.- impurity regions 35a, 35b having a low concentration and n.sup.+ impurity regions 36a and 36b having a high concentration. Ends 37a of the gate electrode 37 in the channel direction are respectively formed just above the n.sup.- impurity regions 35a and 35b having the low concentration with the gate film 32 therebetween. Selective oxide films 41 are formed to connect to the ends 37a of the gate electrode. Due to requirement in a manufacturing process, a natural oxide film 38 is located in the gate electrode 37 so as to form the ends 37a of the gate electrode extending just above the n.sup.- impurity regions 35a and 35b.
According to this GOLD structure, the n.sup.- impurity region to be the drain region is formed to be located just below the gate electrode. Thus, a peak position of the field strength in the proximity of the drain is located just below the gate electrode. Therefore, on applying a predetermined voltage to the gate electrode, the electric field by the gate is applied to the n.sup.- impurity regions. Consequently, even if the electrons generated by the impact ionization flow into the gate oxide film interposed between the gate electrode and the n.sup.- impurity regions, there will be no depletion of the carriers on the substrate surface in the n.sup.- impurity regions because the field by the gate electrode will attract the electrons. This can prevent the reduction of the current drive capacity, i.e., deterioration of the current gain .beta..
However, the field effect transistor having the above-described GOLD structure requires formation of n.sup.- impurity regions in the low concentration as the source/drain regions inside the gate electrode. In other words, it is necessary to form a structure in which the n.sup.- impurity regions forming part of the source/drain regions, and part of the gate electrode are completely overlapped with each other. This structure requires a complicated manufacturing process.
FIGS. 18 to 21 are cross-sectional views showing a manufacturing method of an n-channel MOS transistor having the GOLD structure shown in FIG. 17 in order of process. Referring to FIG. 18, a gate oxide film 32 is formed on a p-type silicon substrate 31. A first polysilicon layer 371 is formed on this gate oxide film 32, having a thickness of 50 nm. After that, a natural oxide film 38 is grown on the first polysilicon layer 371, having a thickness of 5 to 10 .ANG. by air curing of the wafer. A second polysilicon layer 372 is formed on this natural oxide film 38. An oxide film 39 is formed on the second polysilicon layer 372 in accordance with a predetermined pattern by the CVD method.
Referring to FIG. 19, an isotropic dry etching treatment having a high selectiveness is applied to the second polysilicon layer 372, using the oxide film 39 as a mask. The second polysilicon layer 372 is etched such that it is scraped in the portion under the oxide film 39 to form a gate electrode 37, the first polysilicon layer 371 remaining with its surface exposed on opposite sides of the oxide film 39. After that, phosphorus ions having a high energy of about 80 keV are implanted as shown by the arrows, using the oxide film 39 as a mask. These phosphorus ions penetrate the thin first polysilicon layer 371 and reaches the inside of the silicon substrate 31, so that n.sup.- impurity regions 35a, 35b having a low concentration are formed.
As shown in FIG. 20, a sidewall oxide film 40 is formed on opposite sides of the gate electrode 37. The first polysilicon layer 371 remaining outside of the sidewall oxide film 40 is removed by anisotropic dry etching, thereby forming an end 37a of the gate electrode.
After that, as shown in FIG. 21, a selective oxide film 41 is formed to be connected to the end 37a of the gate electrode. At last, n.sup.+ impurity regions 36a, 36b are formed by implanting arsenic ions outside of the sidewall oxide film 40, using the oxide films 39 and 40 as a mask. In this way, a field effect transistor having the GOLD structure is manufactured.
In the manufacturing process shown in the description above of FIG. 19, however, isotropic dry etching is used to cause the thin first polysilicon layer 371 to remain with the surface being exposed. At this time, it is necessary to stop the isotropic etching halfway. It is extremely difficult to effect the control of the completion of this isotropic etching, using the natural oxide film 38. Furthermore, it is extremely difficult to control the amount of etching of the second polysilicon layer 372 in the lateral direction by using isotropic etching so as to accurately provide an effective channel length Leff.
Further, if the gate length decreases to about a quarter micron (0.25 .mu.m) or below with the microminiaturization of the field effect transistor, an effective channel length Leff shown in FIG. 17 will become extremely short. Therefore, it will be difficult to stably form the n.sup.- impurity regions 35a and 35b, which form part of the source/drain regions, just below the ends 37a of the gate electrode. That is, the amount of the overlapping portion between the n.sup.- impurity regions 35a, 35b and the ends 37a of the gate electrode depends on the isotropic etching process of the second polysilicon layer 372 shown in FIG. 19 and the ion-implantation process conducted through the thin first polysilicon layer 371. Therefore, the size of the n.sup.- impurity regions 35a, 35b formed by the ion-implantation is controlled by the amount of etching of the second polysilicon layer 372. Since it is difficult to accurately control the amount of etching in the lateral direction in isotropic etching, it is difficult to control the short effective channel length Leff and the size of the n.sup.- impurity regions 35a, 35b at a desired value in a stable manner.
Therefore, as long as the GOLD structure is employed, it is difficult to implement a field effect transistor having a gate length of a quarter micron order.